Design of Ripple Borrow Subtractor using different logic techniques

Power dissipation has become an overriding concern for VLSI circuits and it may come to dominate the total chip power consumption as the technology feature size shrinks. The main aim of this paper is to minimize the leakage power by using a ultra low leakage techniques. In this work we are choosing the Benchmark circuit as full subtractor . This full subtractor are designed by using different techniques such as conventional CMOS, Pseudo NMOS, transmission gate, Static NMOS, Complementary pass logic, push pull logic, 2T, Sleepy Approach, Stack Approach, Sleepy Stack Approach, Sleepy Keeper. The parameters such as power and area are compared for the above techniques. DSCH3.1 and MICROWIND3.1 Tool is used for simulating above techniques.